The present invention relates to a method of manufacturing a semiconductor device comprising patterning a multilayered structure by etching. The present invention is particularly applicable to accurately etch though non-homogenous films thereby patterning features for high-density semiconductor devices having a design rule of about 0.18xcexc and under.
Fabrication of semiconductor devices begins with providing a semiconductor substrate, usually of doped monocrystalline silicon, and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on the semiconductor substrate to attain individual circuit components. The features and devices are then interconnected to ultimately form an integrated semiconductor circuit by a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as xe2x80x9cdamascenexe2x80x9d-type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or inter-layer dielectric (ILD) between vertically spaced metallization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical-mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that the contact or via and the upper line are formed simultaneously.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an ILD ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. One type of ILD material that has been explored is a group of flowable oxides, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). Such polymers and their use are disclosed in, for example, U.S. Pat. No. 4,756,977 and U.S. Pat. No. 5,981,354. HSQ-type flowable oxides have been considered for gap filling between metal lines because of their flowability and ability to fill small openings. HSQ-type flowable oxides have been found to be vulnerable to degradation during various fabrication steps, including plasma etching.
In fabricating the various semiconductor devices and their integration, it is conventional to employ layers having a concentration variation of one or more components through the layer as, for example, a doped polysilicon layer having a high concentration of dopant near its surface in the formation of a source/drain region or conductive feature. Other common non-homogenous films employed in the manufacture of device layers result from the intended or unintended variation of components in the film as, for example, in the formation of low dielectric constant (low-k) materials useful as interlayer dielectrics.
In etching such non-homogenous layers, the prior art has either ignored the variation of components through the subject layer or employed discrete etching steps, such as the addition of an additional etching component or a discrete change in the concentration of the etchant. However, it would be highly advantageous to develop etching processes that would compensate for the non-homogenous nature of layers that are employed in the fabrication of semiconductor devices or features. It would also be highly advantageous to develop a methodology capable of etching conventional layers employing the same basic etch chemistry to minimize processing variations.
An advantage of the present invention is a method of etching a non-homogenous layer on a semiconductor substrate by continuously varying at least one parameter during etching of the layer to correspond to concentration variations of a non-homogenous layer thereby improving the accuracy and throughput of the etching process.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of etching a non-homogenous film on a semiconductor substrate. The method comprises: forming a non-homogenous layer having a varying concentration of at least one element through the layer on the semiconductor substrate. In an embodiment of the present invention, the non-homogenous layer can comprise a silicate glass layer having a varying carbon concentration through the layer. The silicate glass can be formed on a conductive layer and perform as an interlevel dielectric.
The method continues by etching the non-homogenous layer with an etchant having a reactive agent while continuously varying at least one etch process parameter, such as varying the concentration of the reactive agent in the etchant to correspond to the concentration of the at least one element in the layer during etching through the non-homogenous layer. The present invention advantageously varies the amount of a given agent in an etchant mixture to loosely correspond to the relative amount of a particular component that varies through a non-homogenous layer thereby improving etching accuracy and throughput of non-homogenous layer.
Another aspect of the present invention is a method of etching a composite layer comprising a conductive layer and a silicon oxide film thereon. The method comprises: forming a silicon oxide film having a varying concentration of carbon through the film; forming a layer of photoresist material on the silicon oxide film; patterning the photoresist layer to form a photoresist mask having at least one opening; and using the photoresist mask, etching the silicon oxide film with an etchant having a reactive agent by continuously varying the concentration of the reactive agent in the etchant to correspond to the concentration of the carbon through the film during etching. Advantageously, the present invention improves the etching of non-homogenous ILD layers employed in the formation of interconnects.